The present invention relates to a switching power unit that has an overcurrent protecting function for restricting an output current in a case where electrical overload or output short circuit occurs.
An example of the switching power unit having the overcurrent protecting function is shown in FIG. 11. As to the switching power unit, an input voltage vin smoothed in a capacitor c1 of an input stage is switched by a transistor tr1. During a period in which the transistor tr1 is ON, energy is provided to a coil 11, a capacitor c2, and a load r1 by a voltage vout that appears in an emitter of the transistor tr1. During a period in which the transistor tr1 is OFF, energy accumulated in the coil 11 is refluxed by a diode dl so as to be given to the load r1.
An output voltage vo is controlled in accordance with (a) a feedback voltage vadj obtained by dividing the output voltage vo at a predetermined ratio based on resistance values of resistors r1 and r2, and (b) a reference voltage vref1 of a reference voltage source 2. First, a voltage corresponding to a difference between both the voltages is outputted by a differential amplifier 1, and a comparator 4 compares the voltage with a triangular wave of 100 [kHz] outputted from an oscillator 3. Then, the comparator 4 outputs a PWM signal having a pulse width corresponding to an output level of the differential amplifier 1.
Next, when the PWM signal is given to a drive circuit 5, the drive circuit 5 controls the transistor tr1 so as to be ON/OFF corresponding to a duty cycle of the PWM signal. Thus, the output voltage vo is controlled by a constant voltage (for example, 5 [V]) determined by (a) the reference voltage vref1 and (b) a dividing ratio based on the resistors r1 and r2.
Upon the foregoing operation, as shown by vcmp and vout in FIG. 12, the output voltage of the comparator 4, that is, the PWM signal and the voltage vout have pulse widths indicated in the figure. When ON time and OFF time of the transistor tr1 are indicated by tON and tOFF respectively, a duty D of the transistor tr1 is as follows.                                                         D              =                                                tON                  /                                      (                                          tON                      +                      tOFF                                        )                                                  xc3x97                                  100                  ⁢                                      xe2x80x83                                    [                  %                  ]                                                                                                        =                                                (                                      vO                    /                    vIN                                    )                                xc3x97                                  100                  ⁢                                      xe2x80x83                                    [                  %                  ]                                                                                        (        1        )            
However, when the load r1 is under a heavy-loading condition, a coil current i1 that flows into the coil 11 increases as shown by a difference between the broken line and the continuous line in the figure. When the coil current i1 exceeds an overcurrent detection level ic1, an overcurrent condition is detected by an overcurrent detection circuit 6 provided on the input stage, and a set signal is outputted to an RS flip-flop circuit 7.
The RS flip-flop circuit 7 is set when a set terminal voltage vset is varied to a high level. Once the set terminal voltage vset becomes a high level, the RS flip-flop circuit 7 is latched, so that the output is retained at a low level. At this time, a reset terminal voltage vrst remains at a low level.
Although the output voltage vcmp and the voltage vout of the comparator 4 have pulse widths shown by the broken line in FIG. 12, the pulse widths are shortened as shown by the continuous line because the output of the RS flip-flop circuit 7 remains at a low level since the RS flip-flop circuit 7 has been set. The duty of the transistor tr1 drops in this manner, so that the output voltage vo drops. Thus, the increase in the output current is restricted. Consequently, the output current io drops at A point as shown in FIG. 13.
Further, a reset signal is outputted from the oscillator 3 to the RS flip-flop circuit 7 when the transistor tr1 is OFF, and the reset terminal voltage of the RS flip-flop circuit 7 as shown by vrst in FIG. 12. At this time, once the reset terminal voltage becomes a high level, the RS flip-flop circuit 7 is latched, and the RS flip-flop circuit retains the output at a high level unlike the case where the set terminal voltage becomes high. Thus, under the next ON condition, the transistor tr1 becomes ON at an ordinary timing.
However, in the switching power unit, when switching frequency is made higher (not less than approximately 50 [kHz]) so as to miniaturize the switching power unit and realize light weight etc., disadvantages occur in the operation of the overcurrent protecting function as described below.
That is, as shown in FIG. 12, there occur delays both in td1, a time the set terminal voltage takes to be a high level, and in td2, a time the transistor tr1 takes to turn OFF after the set terminal voltage become a high level. A delay time td, a total of both the td1 and td2, is a time the transistor tr1 takes to turn OFF after the overcurrent detection has been performed, that is, a time the overcurrent protecting function takes to begin operating. The delay time td comes to approximately 1 [xcexcsec]. When the switching pulse width is shortened upon overcurrent protecting operation at the switching frequency of 100 [kHz], that is, at a switching cycle of 10 [xcexcsec], this influences the protecting operation so greatly that this has to be taken into consideration.
For example, supposing that input voltage vin=40[V], and output voltage vo=5[V], and inductance L of coil 11=200 [xcexcH], a current xcex94i that is variation of the coil current i1 at the delay time td is as follows.
xcex94i=[(vinxe2x88x92vo)/L]xc3x97td=0.175[A]xe2x80x83xe2x80x83(2) 
Thus, the coil current i1 exceeds the overcurrent detection level ic1 due to the current xcex94i. Then, the current variation xcex94i increases an average current, that is, the output current io.
An output characteristic at this time, as shown in FIG. 13, is such that an emitter current increases as the load approaches a short circuit condition (vo=0[V]), and the emitter current exceeds an absolute maximum rating value (2.5[A]), so that a drooping characteristic is not realized. The foregoing switching power unit has such a problem that: the overcurrent protecting function does not operate exactly as the switching frequency becomes higher.
Japanese Unexamined Patent Publication No. 46828/1995 (Tokukaihei 7-46828)(Publication date: Feb. 14, 1995) discloses another prior art for solving the foregoing problem. FIG. 14 and FIG. 15 show the prior art. These FIGS. 14 and 15 correspond to the foregoing FIGS. 11 and 13 respectively, and the same reference numerals are given to corresponding portions. It is remarkable that the switching power unit is further provided with a comparator 8, a constant voltage source 9, and an oscillation frequency changing circuit 10 so as to reduce the oscillation frequency in the case where the overcurrent occurs due to the output short circuit.
The voltage vadj obtained by the resistors r1 and r2 is given to a non-inverting input of the comparator 8, and the constant voltage source 9 is connected to an inverting input of the comparator 8. The reference voltage vref1 generated by the reference voltage source 2 is, for example, 1.25[V]. On the other hand, a reference voltage vref2 generated by the reference voltage source 9 is, for example, 0.6[V]. When the feedback voltage vadj to the comparator 8 is 0.6[V], the output voltage vo is as follows.
Vo=0.6[V]xc3x97(r1+r2)/r2=2.4[V]xe2x80x83xe2x80x83(3) 
That is, the comparator 8 detects that the output voltage vo becomes lower than 2.4[V] shown in the foregoing expression. Responding to this, the oscillation frequency changing circuit 10 drops the oscillation frequency of the triangle wave, brought about by the oscillator 3, from 100[kHz] to 20[kHz].
Thus, a resistance value of the load r1 is made smaller by load short circuit etc., so that the output current io increases. When a collector current of the transistor tr1 increases so as to exceed the overcurrent detection level, the overcurrent detection circuit 6 detects the overcurrent condition, so that the overcurrent protecting function begins operating. Then, the RS flip-flop circuit 7 is set by a set signal outputted from the current detection circuit 6. The switching pulse width of the transistor tr1 is shortened, and a time in which the transistor tr1 remains ON is shortened, so that the output voltage vo drops at A point in FIG. 15 as described above.
Further, when the resistance value of the load r1 becomes low, the output voltage vo drops to B point shown in the figure so as to be 2.4[V], and the feedback voltage vadj at this time becomes 0.6[V]. When the output voltage vo further drops and the feedback voltage vadj becomes lower than 0.6[V] of the reference voltage vref2, the output of the comparator 8 that has been a high level becomes a low level, and the oscillation frequency changing circuit 10 outputs a voltage for instructing the oscillator 3 to change the oscillation frequency, so that the oscillator 3 drops the oscillation frequency from 100[kHz] to 20[kHz].
Even though there occurs the following state, that is, even though the switching pulse width is shortened by an ordinary overcurrent protecting operation and the switching pulse width that is determined by the delay time from the overcurrent detection to turning OFF of the transistor tr1 approaches the minimum, the output of the comparator 8 varies at B point and the switching frequency drops, so that the switching pulse width is widened.
For example, the transistor tr1 usually performs switching at a duty D of 5[V]/12[V]≈41.7[%] based on the foregoing expression 1, and when the output voltage vo is 2.4[V] at B point, the duty D is 20[%] based on the expression 1, so that the switching pulse width increases from 2 [xcexcsec] to 10 [xcexcsec]. Therefore, it is possible to reduce the influence exerted by the delay time td in the overcurrent protecting operation by ⅕ in comparison with the prior art.
Thus, as shown in FIG. 15, the output current io returns to a regular overcurrent point from B point, at which the switching frequency fs begins to drop, to C point, at which the switching frequency stops dropping, so that the output current io drops. After passing through C point, the oscillation frequency is fixed at 20 [kHz]. When the load r1 is under a light-loading condition, the switching pulse width is shortened, so that the delay time td have a greater influence. As a result, the output current io increases.
However, as described above, since the output current io is dropped from B point to C point, it is possible to greatly restrict the increase of the output current io. Thus, the output current io does not exceed the absolute maximum rating 2.5[A]. Note that, in FIG. 15, the broken line indicates the overcurrent protecting characteristic shown in FIG. 13.
While, it is still required to realize miniaturization and a low cost of the switching power supply. In order to realize the miniaturization and the low cost, it is effective that the switching power unit including the transistor tr1 is made as an integrated circuit and the coil 11 and a capacitor c2 externally provided on the integrated circuit are miniaturized. Then, a step of making the switching frequency fs higher can be employed. While, also a bipolar element of a comparatively reasonable price can cover 300 [kHz], the switching frequency fs as the integrated circuit.
However, also in the prior art shown in FIG. 14, when the respective voltages are such that vin=24[V], vo=5[V], the duty D under an ordinary operation condition is approximately 20.8[%] based on the expression 1, and fs=300 [kHz] (switching cycle T=3.33 [xcexcsec], and ON time tON is as follows.
tON=Txc3x97D=3.33xc3x970.208=693[nsec]xe2x80x83xe2x80x83(4) 
As a result, the ON time tON becomes shorter than 1 [xcexcsec], the delay time td.
Thus, as shown by a virtual line (chain line) in FIG. 15, even though the overcurrent is detected at A point and the protecting operation is performed, the protecting operation is performed after the ON time tON has passed in the transistor tr1, so that the overcurrent protecting operation is nullified. As a result, the output current io increases. Further, when the load r1 is under a heavy loading condition and the output current io increases so as to exceed the capacity of the transistor tr1, for example, 3.0[A], a voltage drop VCE between the collector and the emitter of the transistor tr1 begins increasing, and a damage of the transistor tr1 increases, so that the efficiency drops. As a result, the output voltage vo begins to drop. When the voltage at D point is vo=2.4[V], the switching frequency fs drops due to the operation of the oscillation frequency changing circuit 10, so that an ordinary overcurrent protecting operation is performed. As a result, the voltage comes to C point.
That is, although the overcurrent protecting operation is performed after passing through C point, that is, after the short circuit protecting operation is performed between D to C points, the overcurrent protecting operation is not performed between A to D points. Further, the increase in the voltage drop VCE gives more damage to the transistor tr1, so that it is required to widen an area for safety operation (ASO) of the transistor tr1. As a result, there occurs such a problem that the size and cost of the transistor tr1 are increased.
Then, in order to solve the foregoing problem, still another prior art is proposed in Japanese Unexamined Patent Publication No. 245142/2000 (Tokukai 2000-24514 2)(Publication date: Sep. 8, 2000). The prior art is shown in FIG. 16. In a structure of FIG. 16, the same reference numerals are given to portions that are similar to and correspond to portions shown in FIG. 11 and FIG. 14, and descriptions thereof are omitted. It is remarkable that, in the prior art, a second oscillation frequency changing circuit 10b corresponds to the oscillation frequency changing circuit 10 in the structure of FIG. 11 and FIG. 14, and there is provided a first oscillation frequency changing circuit 10a which drops the oscillation frequency of the oscillator 3 in response to the overcurrent detection circuit 11.
The oscillator 3 drops the oscillation frequency from a first oscillation frequency such as 300 [kHz] to a second oscillation frequency such as 100 [kHz] in response to an output of the first oscillation frequency changing circuit 10a. The oscillator 3 drops the oscillation frequency from 100 [kHz] that is the second oscillation frequency to 20 [kHz] that is a third oscillation frequency in response to an output of the second oscillation frequency changing circuit 10b. 
Thus, as shown in FIG. 17, the oscillator 3 operates at fs=300 [kHz] under an ordinary loading condition, and when the load r1 is under a heavy loading condition, and the resistance value of the load r1 becomes small, and the output current io increases, and the collector current of the transistor tr1 increases, and the collector current exceeds the overcurrent detection level of 2[A] at A point of FIG. 17, the overcurrent detection circuit 6 detects the overcurrent condition so as to start the overcurrent protecting operation, and the first oscillation frequency changing circuit 10a switches to the operation at fs=100 [kHz]. Further, the RS flip-flop circuit 7 is set, and the switching pulse width of the transistor tr1 is shortened, and the ON time of the transistor tr1 becomes short, so that the output voltage vo drops at A point.
Further, when the resistance value of the load r1 becomes small, the output voltage vo drops to B point so as to be 2.4[V], so that the feedback voltage vadj becomes 0.6[V]. When the output voltage vo further drops and the feedback voltage vadj becomes smaller than 0.6[V] of the reference voltage vref2, the second oscillation frequency changing circuit 10b switches to the operation at fs=20 [kHz]. Even though there occurs the following state, that is, even though the switching pulse width is shortened by an ordinary overcurrent protecting operation and the switching pulse width that is determined by the delay time td approaches the minimum, the switching frequency drops again at B point, so that the switching pulse width is widened. Thus, the output current io drops from B point, at which the switching frequency fs begins to drop, to C point, at which the drop comes to an end, so as to return to the regular overcurrent point 2[A].
Since the oscillation frequency is fixed at 20 [kHz] after passing through C point, the switching pulse width is shortened when the load r1 becomes smaller, and the delay time td has such a great influence that the output current io increases. However, since the output current io is made to drop in advance from B point to C point, it is possible to restrict the increase in the output current io greatly. Thus, the output current io does not exceed the absolute maximum rating, 2.5[A] for example. Note that, in FIG. 17, the broken line shows the overcurrent protecting characteristic in a case where the switching frequency fs is fixed so that fs=100 [kHz].
In this manner, the switching frequency is made to drop not only at a time when the output voltage vo drops due to the output short circuit etc. but also at a time of the overcurrent detection, so that the switching frequency fs under a normal loading condition is heightened to 300 [kHz], the upper limit in the operation frequency of the transistor tr1. Further, the external coil 11 and the capacitor c2 are miniaturized. Thus, miniaturization and a low cost of the switching power unit are realized.
In the switching power unit arranged in the foregoing manner, a time constant circuit with a capacitor is used in switching the switching frequency so as to prevent hunting. This is illustrated in FIG. 18. FIG. 18 is an electric circuit diagram showing a concrete structure of the first oscillation frequency changing circuit 10a and the second oscillation frequency changing circuit 10b. Note that, FIG. 18 shows a resistor r11 and a transistor q11, that partially constitute the overcurrent detection circuit 6, and a constant current circuit 3a in the oscillator 3. An output current i40 from the constant current circuit 3a is given to the oscillator circuit, and the oscillator circuit oscillates at a frequency corresponding to the current i40.
First, the first oscillation frequency changing circuit 10a is provided with a constant current source f21, a capacitor c21, transistors q21 to q24, resistors r21 and r22. A series circuit of the constant current source f21 and the capacitor c21 intervene between a power line 12 to which the power voltage vs is given and a ground line 13. Also, there are provided (a) a series circuit of the resistor r21 and the transistor q21 and (b) a series circuit of the transistor q23 generating a constant current i21, the resistor r22, and the transistor q22, between the power lines 12 and 13 so that the series circuits are connected to each other. The transistor q11 is provided in parallel to the capacitor c21, and an output voltage of the capacitor c21 is given to a base of the transistor q21. A connecting point between the resistor r21 and the transistor q21 is connected to a base of the transistor q22. The diode-connected transistor q23 constitutes a current mirror circuit in combination with the transistor q24.
Thus, the transistor q11 is OFF under a rated-load condition, and the capacitor c21 is charged by the constant current source f21, and the charging voltage causes the transistor q21 to be ON, and the transistor q22 becomes OFF so that the current i21 becomes 0, and the output current i22 from the transistor q24 also becomes 0. On the other hand, when the overcurrent condition causes the transistor q11 to be ON, charges charged in the capacitor c21 are discharged, and the transistor q21 becomes OFF, and the transistor q22 becomes ON so that the current i21 flows, and the output current i22 flows from the first oscillation frequency changing circuit 10a to a constant current generating circuit 3a. of the oscillator 3
Here, an emitter area ratio of the transistors q23 and q24 is 1:1, and 2.6[V] is selected for the power voltage vs, and 46 [k"PHgr"] is selected for the resistance value of the resistor r22. Thus, the relationship of them is as follows.
i22=i21=(vsxe2x88x92VBExe2x88x92VSAT)/r22xe2x80x83xe2x80x83(5) 
Here, VBE is a voltage between the base and the emitter of the transistor q23, for example, the voltage is 0.65[V]. Further, VSAT is a saturation voltage in a case where the transistor q22 is ON, for example, the voltage is 0.1[V]. Thus, based on the expression (5), it is possible to cause a current of i22=40 [xcexcA] to flow.
The second oscillation frequency changing circuit 10b is provided with transistors q31 to q34, resistors r31 and r32, and a constant current source f31. The constant current source f31 provides a constant current i31 to emitters of the transistors q31 and q32 constituting a pair of differentials. The feedback voltage vadj is given to a base of the transistor q31, and a collector is grounded. A reference voltage vref3 generated by the resistors r31 and r32, dividing voltages, which intervene between the power lines 12 and 13, for example, a voltage of 0.6[V] is given to a base of the transistor q31. A collector of the transistor q32 is grounded via the diode-connected transistor q33. The transistor q33 constitutes a current mirror circuit in combination with the transistor q34.
An emitter ratio of the transistors q33 and q34 is set to 1:3, and the current is set to i31=20 [xcexcA]. Thus, when vo=5[V] under a normal loading condition, vadj=1.25[V] and vref3 less than vadj, and the transistor q31 becomes OFF, and the transistors q32 and q33 become ON, and the transistor q34 can draw a current of 60 [xcexcA].
The constant current generating circuit 3a is provided with transistors q41 to q48, diodes d41 to d44, and a constant current source f41. A series circuit of the constant current source f41 and the diode-connected transistor q41 intervenes between the power lines 12 and 13, and the series circuit generates a constant current i41. The transistor q41 constitutes a current mirror circuit in combination with the transistors q42, q43, and q44, and an emitter ratio of the respective transistors q41, q42, q43, and q44 is 1:1:2:1.
The transistor q42 constitutes a series circuit for generating the output current i40 in combination with a diode-connected transistor q45, diodes d41 and d42 so that the series circuit intervenes between the power lines 12 and 13. A series circuit of the diode d42 and the transistor q42 is provided in parallel to the series circuit of the diode d43 and the transistor q43. An output current i22 from the first oscillation frequency changing circuit 10a flows into a collector of the transistor q43.
Further, the transistor q44 is connected to a diode-connected transistor q46 in series, and intervenes between the power lines 12 and 13. While, a series circuit of the transistor q45 and the diode d41 is provided in parallel to the series circuit of the transistor q47 and the diode d44. The transistor q46 and a transistor q47 constitute a current mirror circuit. Thus, a current whose amount is in proportion to an amount of the i44 flowing in the transistor d44 is supplied by the transistors q46 and q47 so as to flow into a cathode side of the diode d41. A collector of the transistor q47 is connected to a collector of the transistor q34.
An emitter area ratio of the transistor q46 and the transistor q47 is set to 1:0.8. The current i41 provided from the constant current source f41 to the transistor q41 is set to 10 [xcexcA]. Thus, currents i42 and i44 flowing in the transistors q42 and q44 are respectively 10 [xcexcA], and a current i43 flowing in the transistor q43 is 20 [xcexcA], and a current i145 flowing in the transistor q47 is 8 [xcexcA]. A current corresponding to a current i46 flowing in the transistor q45 is made to flow by the transistor q48 which constitutes a current mirror circuit in combination with the transistor q45 at an emitter ratio of 1:1, and is outputted as the output current i40.
In the constant current generating circuit 3a arranged in this manner, the transistor q24 becomes OFF under a normal loading condition, and the current is i22=0 [xcexcA]. At this time, the transistor q34 becomes ON, and the current i45 flowing in the transistor q47 is sufficiently drawn by the transistor q34, so that there is formed a bypass extending from the transistor q47 via the transistor q34 to 13. Thus, the relationship between them is as follows.
i40=i46=i42+i43=30[A]xe2x80x83xe2x80x83(6) 
Next, when the overcurrent condition is detected, the transistor q24 becomes ON, so that the current i22 is provided. Since the current i22 which is allowed to pass by the transistor q24 is larger than the current i43 which is allowed to pass by the transistor q43, a collector potential of the transistor q43 becomes a high level of vs-VSAT, so that the diode d43 becomes OFF. Thus, the relationship between them is as follows.
i40=i46=i42=10 [xcexcA]xe2x80x83xe2x80x83(7) 
Note that, at this time, the transistor q34 remains ON.
Further, when the output voltage vo drops so as to be not more than 2.4[V] (vadj=0.6[V]), the transistor q34 becomes OFF. Thus, the current i45 flowing in the transistor q47 flows into a cathode side of the diode d41, and the relationship between them is as follows.
i40=i46=i42xe2x88x92i45=2 [xcexcA]xe2x80x83xe2x80x83(8) 
Here, supposing that an oscillation frequency fs of an oscillating circuit (not shown) is capacitance Cocs of an oscillation capacitor and an amplitude of an oscillation wave form is Vosc, the relationship between them is as follows.
fs=1/T=140/2Coscxc3x97Voscxe2x80x83xe2x80x83(9) 
Thus, supposing that Cosc=50 [pF] and Vosc=1[V], the oscillation frequency fs is 300 [kHz] in the case where i40=30 [xcexcA], and the oscillation frequency fs is 100 [kHz] in the case where i40=10 [xcexcA], and the oscillation frequency fs is 20 [kHz] in the case where i40=2 [xcexcA].
Here, in the first oscillation frequency changing circuit 10a, the current i23 provided from the constant current source f21 is, for example, set to 1 [xcexcA], and the capacitance of the capacitor c21 is set to 150 [pF]. A current passing through the transistor q11 is, for example, of an [mA] order. Thus, a time taken to perform OFF operation of the transistor q21 is shorter than approximately 3 [xcexcsec] which is a switching cycle in an operation at fs=300 [kHz], for example, the OFF operation is completed in approximately 20 [nsec]. On the other hand, an ON operation of the transistor q21 requires the delay time tdf1 taken for the constant current source f21 to charge the capacitor c21 up to an ON voltage (VBE=0.65 [V]) of the transistor q21. The delay time tdf1 is as follows.                                                         tdf1              =                              xe2x80x83                            ⁢                                                (                                      C21                    *                                          V                      BE                                                        )                                /                I23                                                                                        =                              xe2x80x83                            ⁢                                                (                                                            150                      ⁢                                              xe2x80x83                                            [                                              μ                        ⁢                                                  xe2x80x83                                                ⁢                        F                                            ]                                        *                                          0.65                      ⁢                                              xe2x80x83                                            [                      V                      ]                                                        )                                /                                  1                  ⁡                                      [                                          μ                      ⁢                                              xe2x80x83                                            ⁢                      A                                        ]                                                                                                                          ≈                              xe2x80x83                            ⁢                              101                ⁢                                  xe2x80x83                                [                                  μ                  ⁢                                      xe2x80x83                                    ⁢                  sec                                ]                                                                        (        10        )            
Thus, the delay time tdf1 is sufficiently longer than 10 [xcexcsec], a switching cycle in operation at fs=100 [kHz]. Thus, in the case where an overcurrent occurs, the switching frequency fs is quickly dropped. Released from the overcurrent condition, the transistor q21 becomes OFF after a time equal to 10 cycles/100 [kHz] elapsed, and the operation is automatically restored to an operation at fs=300 [kHz]. The capacitance etc. of the constant current i23 and the capacitor c21 are suitably set corresponding to the switching frequency fs and a desired delay time tdf1 etc.
As described above, in the switching power unit, the external coil 11 and the capacitor c2 are miniaturized, but the capacitor c21 formed in the integrated circuit requires capacitance to some extent, so that there occurs such a problem that a chip size becomes large. Note that, since the second oscillation frequency changing circuit 10b switches a frequency of the oscillator 3 based on the feedback voltage vadj that has been smoothed in the capacitor c2, the foregoing time constant circuit for preventing hunting is not required.
The object of the present invention is to provide a switching power unit by which it is possible to miniaturize externally provided parts by enabling a switching frequency to be switched and it is possible to miniaturize an integrated circuit itself.
In order to achieve the foregoing object, a switching power unit of the present invention is arranged so that: overcurrent protecting means shortens a switching pulse width so as to restrict an output current when an overcurrent is detected. In the switching power unit, when an overcurrent condition is detected by overcurrent detection means, first oscillation frequency dropping means drops an oscillation frequency of oscillating means from a first oscillation frequency under a normal condition to a second oscillation frequency, and when the overcurrent detection means detects that an output voltage becomes lower than a predetermined level due to the output short circuit etc., second oscillation frequency dropping means drops the second oscillation frequency to a third oscillation frequency.
Therefore, a switching pulse width under a normal condition is short at the first oscillation frequency, so that the switching pulse width sometimes cannot be shortened any more due to the overcurrent protecting operation. However, at the second oscillation frequency, an ON period of the switching element becomes longer than a delay time the switching element takes to turn OFF after the overcurrent condition is detected, so that the overcurrent protecting operation is efficiently performed, thus reducing the output current. Similarly, at the third oscillation frequency, the switching pulse width that has been shortened due to the overcurrent protecting operation is made wider again after the oscillation frequency is dropped from the first oscillation frequency to the second oscillation frequency, so that less influence is exerted by the delay time. Thus, it is possible to prevent increase in the output current brought about by the delay time.
Further, the overcurrent detection output from the overcurrent detection means is given to the first oscillation frequency dropping means via latching means that latches for a period longer than the delay time. Thus, even though a switching pulse is outputted at the first oscillation frequency, the overcurrent detection output is retained, so that the oscillation frequency of the oscillating means is dropped without fail. Then, the oscillation frequency of the oscillating means is restored to the first oscillation frequency after the unit is released from the overcurrent condition and the output voltage smoothed by a capacitor in an output stage is restored to a normal voltage, so that it is not necessary to provide a time constant circuit which prevents hunting. Thus, not only external parts but also a chip size of an integrated circuit itself can be miniaturized.
Further, the switching power unit of the present invention is arranged so that: the second oscillation frequency dropping means sets a level of an output voltage for dropping the second oscillation frequency to the third oscillation frequency according to an input voltage.
Therefore, when the input voltage is large, the oscillation frequency is dropped from a high output voltage, and when the input voltage is small, the oscillation frequency is dropped from a low output voltage, so that it is possible to improve a remarkable decrease/increase characteristic of a current value in a case of a short circuit.
Furthermore, the switching power unit of the present invention is arranged so that: there is provided adjusting means for changing the oscillation frequency according to the input voltage and the output voltage in response to the second oscillation frequency dropping means.
Therefore, when the input voltage is larger than the output voltage, the pulse width is short, so that it is necessary to make the second oscillation frequency lower in particular. If the oscillation frequency is made lower when the output voltage is large, the load current becomes too small, so that it is sometimes desirable that the oscillation frequency is not made lower. With respect to this, it is possible to set the oscillation frequency more appropriately.
Further, the switching power unit of the present invention is arranged so that: there is provided delaying means for forbidding that the first oscillation frequency dropping means change the oscillation frequency upon activation, in relation to the first oscillation frequency dropping means.
Therefore, it is possible to avoid an undesired overcurrent protecting operation brought about by an incoming current of an output capacitor of a large volumetric/low series equivalent resistor upon activation so as to supply the load current sufficiently.
Furthermore, the switching power unit of the present invention is arranged so that: there is provided retaining means for retaining an overcurrent detection output of the latching means, between the latching means and the first oscillation frequency dropping means, in relation to the first oscillation frequency dropping means.
Therefore, even though the switching element is OFF-driven by means of the overcurrent protecting means and the overcurrent detection means does not detect an overcurrent condition temporarily, it is possible to retain the oscillation frequency so that the oscillation frequency remains dropped, so that it is possible to stabilize a pulse width and a cycle of the switching pulse.
Moreover, the switching power unit of the present invention is arranged so that: there is provided dividing means for dividing a reset signal in relation to the latching means.
Therefore, it is possible to stabilize the switching frequency under an overcurrent condition not at the oscillation frequency but at a reset signal frequency.
For a fuller understanding of other object, the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.